1. Field of the Invention
The present invention relates to a gain stage having a switch action condensor and an offset voltage elimination method.
2. Description of the Related Art
Generally it is very effective to use a condensor and not to use a simple resistor as the component to obtain controllability of the gain of a gain stage having an OP-amp. FIG. 1 is a circuit diagram showing an example of the gain stage mentioned in U.S. Pat. No. 4,404,525. In FIG. 1, an input terminal 1 is coupled to one node X of a condenser 15 through an MOS switch 13, and a reference input terminal 29 is also coupled to the node X through an MOS switch 25. The other node Y of the condenser 15 is coupled to an inverting input node 7 of an OP-amp 5, and a reference input terminal 30 is coupled to a non-inverting input node 9 of the OP-amp 5. An output node 11 of the OP-amp 5 is coupled to an output terminal 3. Also, the output node 11 and the input node 7 of the OP-amp 5 are coupled through an MOS switch 17 and through the serial connection of an MOS switch 21 and a condensor 19. A reference input terminal 31 is coupled to node Z through an MOS switch 27. Each of the MOS switches has a control gate, and control signal .phi.10 is input the control gate of the MOS switches 17,25,27, and control signal .phi.20 is input the control gate of the MOS switches 13,21.
The control signals .phi.10, .phi.20 turn the MOS switches OFF at the time of "L" level, and ON at the time of "H" level. FIG. 2 is a timing diagram where the control signals .phi.10, .phi.20 are shown, and FIG. 2 is divided into an initialize period and an output period.
In the initialize period (from t0 to t3), the control signal .phi.20 is "L" level, thus the MOS switches 13,21 are OFF. At time t0, the control signal .phi.10 is at the "H" level, so the MOS switches 17,25,27 are turned ON. The node X is charged to the reference input voltage level(Vref) through the MOS switch 25, the node Z is charged to Vref through the MOS switch 27, and the node Y is charged to Vref plus the characteristic offset voltage level(Voff) of the OP-amp 5 (Vref+Voff) through the MOS switch 17, so that the OP-amp 5 outputs Vref+Voff since it acts as a voltage follower circuit due to the connection of the output node 11 with the inverted input node 7 through the MOS switch 17. At time t2, .phi.10 drops to the "L" level and the MOS switches 17,25,27 turn OFF.
In the output period (from t3 to t5), the control signal .phi.10 is at the "L" level and the MOS switches 17,25,27 are still in the OFF-state. At time t4 the control signal .phi.20 rises to the "H" level, so the MOS switches 13,21 turn ON. So, the input voltage level(Vin) is applied to the node X through the MOS switch 13, and the output voltage level(Vout) is applied to the node Z through the MOS switch 21. During this period, the node Y is in High-Impedance-state.
The charge on the condensers 15,19 is determined by the below equations, where q1 is the charge of the condensor 15 in the initialize period, Q1 is the charge of the condensor 15 in the output period, and q2 and Q2 describe the charge on the condensor 19 at same conditions mentioned for the condensor 15. C1 and C2 are the respective capacitances of the condensors 15, 19.
In the initialize period: EQU q1=C1*((Vref+Voff)-Vref) Equation (1) EQU q2=C2*((Vref+Voff)-Vref) Equation (2)
In the output period: EQU Q1=C1*((Vref+Voff)-Vin) Equation (3) EQU Q2=C2*((Vref+Voff)-Vout) Equation (4)
According to the law of charge conservation, the following equation holds. EQU (1)+(2)=(3)+(4) Equation (5)
Thus, EQU Vout=Vref+(C1/C2)*(Vref-Vin) Equation (6)
So, as Voff is missing from equation (6), the offset voltage is eliminated in this circuit.
In one particular case of above, in which Vref is GND level (0V), equation (6) is simplified as below. EQU Vout=-(C1/C2)*Vin Equation (7)
And in more particular case, C1=C2, equation (7) is simplified as below. EQU Vout=-Vin Equation (8)
As equation (8) the gain stage is also used as simple inverting amp which eliminates the offset voltage.
However, in the gain stage mentioned above there is the following problem. FIG. 3 is an example of a timing diagram showing the problem. In the initialize period, the nodes X,Z are charged to Vref, and the node Y is charged to Vref+Voff by the output 11 of the OP-amp 5. When the control signal .phi.10 rises to "H" level, then the nodes X,Z are charged to Vref, and the node Y is charged to the latest output level of the gain stage, and after that the node Y is charged to Vref+Voff by OP-amp 5. During charging of the node Y, both of the condensors 15,19 act as a capacitive load for the OP-amp 5. So the charging speed is slower than the speed determined by slew rate of the OP-amp 5. On this account, a method of shortening the initialize period may consist of improving the slew rate of OP-amp 5. Using the slew rate to determine the electrical voltage change velocity of above the node Y is good if the operating current of the OP-amp 5 can be increased to shorten the charging time. In the present situation where low power consumption is required, however, this method is not practical.
The characteristic offset voltage Voff needs to be applied to the node Y, between the condensers 15,19 shown in FIG. 1, to remove the characteristic offset voltage of the OP-amp 5 as explained with the above technique. Accordingly, in the initialize period, the nodes X and Z need to be set to Vref. But, a certain amount of time is necessary because in actuality the Vref supply has input impedance and there is the electric wiring resistance in an MOS integrated circuit, before the nodes X and Z becomes stable at Vref.